A customary plasma display panel (PDP) device is composed of a display panel and a driving circuit. The PDP includes a plurality of discharge cells where each has three electrodes. The driving circuit is for driving the three electrodes of each discharge cell, respectively, in accordance with driving method and driving procedures. The three electrodes in each discharge cell include an address electrode (A-electrode) and two discharge sustain electrodes, respectively. The two discharge sustain electrodes can be distinguished into a scan electrode (Y-electrode) and a common electrode (X-electrode).
Some papers regarding driving circuit of the PDP are referenced herein and listed as follows: the U.S. Pat. Nos. 5,446,344 and 5,541,618.
Hereinafter, a prior art regarding PDP is disclosed. FIG. 1A shows a sectional diagram of a cell in a plasma display panel, and FIG. 1B schematically shows a structure (electrodes and n.times.m dots) of a plasma display panel. Note that FIG. 1A shows a cell forming a pixel at an intersection of the "i"th line (Yi) and "j"th column (Aj) of a surface discharge plasma display panel (PDP) having three electrodes shown in FIG. 1B.
In FIG. 1A, reference numeral 11 denotes a rear glass substrate, 12 denotes a dielectric layer, 13 denotes a MgO protective film, 14 denotes a front glass substrate, 15 denotes a fluorescent material (dielectric phosphor) deposited between the walls, 16 denotes a partition wall, and 17 denotes a discharge cavity. Further, reference mark Aj denotes an address electrode, and X and Yi denote sustain electrodes. Note that paired sustain electrodes X and Yi extend perpendicular to the plane of the figure.
As shown in FIG. 1A, sustain electrodes X and Yi are formed on the glass substrate 11 and is covered with the dielectric layer 12 for accumulating wall charges. The dielectric layer 12 is covered with the MgO protective film 13. The address electrode Aj extends in parallel with the plane of the figure and is formed on a glass substrate 14 that faces the glass substrate 11. The address electrode Aj is covered with a dielectric phosphor 15. The partition wall 16 is formed on the glass substrate 14 along a boundary of the pixel. The discharge cavity 17 is defined between the MgO protective film 13 and the phosphor 15. Penning mixtures such as Ne+Xe are sealed in the discharge cavity 17.
As shown in FIG. 1B, the PDP has "n.times.m" pixels with i=1 to n and j=1 to n. In order to turn ON and OFF a cell (pixel) formed at an intersection of an optional one of the sustain electrodes Yi and an optional one of the address electrodes Aj, the sustain electrodes Y1 to Yn are insulated from one another, and the address electrodes A1 to Am are insulated from one another. The sustain electrodes X extend in parallel with the sustain electrodes Y1 to Yn, respectively, and all of the sustain electrodes X are connected together with their one ends.
Present-day driving method of the PDP device usually divides a frame into eight sub-fields SF1 to SF8, as shown in FIG. 2. The ratio of the discharge sustain periods of the sub-fields SF1 to SF8 is 1:2:4:8:16:32:64:128 to realize 256 shades of gray. In FIG. 2, reference numerals 1 to N denote the discharge sustain electrodes Y1 to Yn.
If a screen is written at 60 Hz, a frame will be maintained for 16.6 microseconds. If one frame involves 510 discharge sustain cycles (each with two times of discharge), the numbers of discharge sustain cycles in the sub-fields SF1 to SF8 are 2, 4, 8, 16, 32, 64, 128, and 256, respectively. If the period of the discharge sustain is 8 nanoseconds, the total discharge sustain period in one frame will be 4.08 microseconds.
FIGS. 3A and 3B are to disclose a driving method of a three-electrode surface-discharge type PDP device. Like present-day driving method of the PDP device, the driving method also divides a frame into several sub-fields. In FIGS. 3A and 3B, (i), (ii) and (iii) are voltage waveforms applied to the address electrodes Aj, discharge sustain electrodes X and discharge sustain electrodes Yi, respectively, during the reset period and address period of one frame in accordance with the driving method.
In normal discharge cells, processes (a) and (b) completely neutralize wall charges or reduce them to an extent that no display errors occur due to the remnant wall charges. On the other hand, due to defects induced during the manufacturing of the PDP, some discharge cells may have abnormal properties to cause insufficient self-erase discharge and leave a large quantity of wall charges, or achieve no self-erase discharge, to leave wall charges accumulated by total write discharge as they are. These abnormal cells unnecessarily emit light during the discharge sustain period even with no address discharge. Accordingly, the driving method forcibly discharges and erases these wall charges before address discharge, to thereby prevent unnecessarily lighting during the discharge sustain period and improve the display quality of the PDP.
Next, during process (c), all electrodes are set to 0V, and a pulse of Vs is applied to the sustain electrodes Y1 to Yn. In response to this pulse, the discharge cells that hold a discharge sustain enabling quantity of negative wall charges on the sustain electrodes X relative to the sustain electrodes Yi cause discharge. This discharge may invert the polarity of the wall charges, to accumulate positive wall charges on the sustain electrodes X and negative wall charges on the sustain electrodes Yi. It is not always necessary to equalize the potential Vs with the potential of a sustain pulse during the discharge sustain period if the following equation (1) is satisfied: EQU Vsmin&lt;=Vs&lt;Vfxymin (1)
where Vsmin is a minimum voltage at which all discharge cells in the PDP maintain discharge sustain, and Vxymin is a minimum discharge start voltage between the sustain electrodes X and Y1 to Yn.
During process (d), all electrodes are set to 0V, and a pulse of Va is applied to the sustain electrodes X and a pulse of -Vy to the sustain electrodes Y1 through Yn. The potential of this pulse is the same as that applied to the sustain electrodes X and Yi during the address period. This voltage must satisfy the following equation: EQU Vsmin&lt;=Va+Vy&lt;Vfxymin (2)
In response to the pulse, the discharge cells in which a discharge enabling quantity of positive wall charges are accumulated on the sustain electrodes X relative to the sustain electrodes Y cause discharge. Due to this discharge, the polarity of the wall charges is inverted to accumulate negative wall charges on the sustain electrodes X and positive wall charges on the sustain electrodes Y.
The polarities of the remnant wall charges are integrated by the discharge of processes (c) and (d). In addition, the discharge in processes (c) and (d) uniformly distributes wall charges. The voltage of the next erase pulse is added to the wall charges, to adjust the quantity of the wall charges into one that is sufficient to discharge the wall charges.
During process (e), all electrodes are set to 0V, and an erase pulse 230 of Vs is applied to the sustain electrodes Y1 to Yn. This pulse gently rises. At the same time, a pulse of Vaw is applied to the address electrodes A1 to Am. This results in mostly erasing the wall charges even if a discharge start voltage varies from cell to cell. Only a small quantity of wall charges will be left. The remnant wall charges are positive opposite to the polarity of the next address pulse, to prevent unnecessary address discharge or lighting, thereby improving the display quality. The reason why the pulse of Vaw is applied to the address electrodes A1 to Am is to prevent unnecessary discharge between the sustain electrodes Y1 to Yn and the address electrodes A1 to Am.
Then, the address period starts. The address pulse of Va is continuously applied to the address electrodes A1 to Am. The scan pulse of -Vsc is continuously applied to the sustain electrodes Y1 to Yn. The sustain electrodes X are set to Va.
During process (f), the address electrodes A1 to Am are set to Vaw, and a sustain pulse of Vs is alternately applied to the sustain electrodes X and Y1 to Yn. The number of the sustain pulses is determined in accordance with the sub-fields actually needed.
FIG. 4 is an example of a three-electrode surface-discharge AC type PDP device which employs the plasma display panel of FIG. 1 and the aforesaid driving method. FIG. 4 is a block diagram showing the relationship between the plasma display panel and driving circuit. In FIG. 4, reference numeral 21 denotes a plasma display panel, 22 denotes a power source circuit, 23 denotes an address driver, 24 denotes a Y-common driver, 25 denotes a scan driver, 26 denotes an X-common driver, and 27 denotes a control circuit.
The display panel 21 has a first glass substrate on which address electrodes A1 to Am are arranged in parallel. A second glass substrate faces the first glass substrate and holds sustain electrodes X and Y1 to Yn that are orthogonal to the address electrodes A1 to Am. The sustain electrodes X form pairs with the sustain electrodes Y1 to Yn. All of the sustain electrodes X are connected together with their one ends.
As shown in FIG. 4, the power source circuit 22 generates voltages which are applied to the electrodes through the address driver 23, Y-common driver 24, scan driver 25, and X-common driver 26. The address driver 23, Y-common driver 24, scan driver 25, and X-common driver 26 are controlled in response to signals provided by the control circuit 27. Note that the control circuit 27 generates these signals according to externally supplied display data DATA (under resolution of 8-bit and 256 shades of gray), a dot clock signal CLOCK synchronous to the display data DATA, a vertical synchronous signal VSYNC, and a horizontal synchronous signal HSYNC.
The address driver 23 has a shift register 231 having a serial data input end for receiving serial display data from the control circuit 27, a clock input end for receiving a shift pulse from the control circuit 27, a latch circuit 232 for latching parallel display data stored in the shift register 231 after the shift register 231 secures display data for a line, and an address electrode drive circuit 233 to be turned on or off in response to an output of the latch circuit 232 and to provide a drive voltage in response to a control signal from the control circuit 27. The address electrode drive circuit 233 has m output ends connected to the address electrodes A1 to Am, respectively.
The scan driver 25 has a Y-drive circuit 251 distinguished into N Yi-drive circuit 251i which are arranged into a serial data input end for receiving "1" in synchronism with the start of an address period in each sub-field. The Y-drive circuit 25 has a clock input end for receiving a shift pulse synchronous to an address cycle. The scan driver 25 also has a Y-drive circuit 252 that is turned ON or OFF in response to output bits from the Y-drive circuit 251 and provides a drive voltage in response to a control signal from the control circuit 27. The Y-drive circuit 252 is distinguished into N Yi-drive circuits 252i which each has output ends connected to the sustain electrodes Y1 to Yn, respectively. The Y-common driver 24 provides a common drive voltage to the sustain electrodes Y1 to Yn through the Y-drive circuit 252. Note that, in FIG. 4, potential Vcc is provided for logic circuits, and potential Vd is provided for drive circuits.
At present, there are many problems desirable to be solved for the PDP device, e.g., enhancement of luminous efficiency, lowering of manufacturing cost, improvement of driving method, lowering of power consumption, and so on, special for lowering of power consumption. It is well known that the power consumed by the PDP device mostly converts into heat, and that the converted heat will affect significantly display quality of the PDP device. The current research for display panels gravitate towards flat display panels. Therefore, the study regarding heat sink lowering of power consumption of the PDP device becomes important more and more.
Accordingly, an objective of the invention is to improve the driving circuit of the PDP device, and in particular, to improve the scan driving circuit which is a complicated part in the driving circuit of the PDP device. The improvement of the scan driving circuit is to lower power consumption thereof, and to further assure the display quality of the PDP device. The details and shortcomings of the driving circuit of the PDP device, according to the prior art, will be further set forth in the analysis of the prior art.